1. Field
Exemplary embodiments of the present invention relate to technology for controlling a buffer configured to receive a high-speed signal and a low-speed signal through a channel.
2. Description of the Related Art
A buffer is a circuit configured to receive a signal inputted to an integrated circuit. In general, a buffer capable of receiving (recognizing) a signal inputted at high speed (i.e., a signal of high frequency) consumes a large amount of current, and a buffer which does not receive a signal inputted at high speed but is capable of receiving a signal inputted at low speed (i.e., a signal of low frequency) consumes a small amount of current.
An I/O pin of a flash memory may receive a command and an address which are low-speed signals and may receive data which are high-speed signals. When a high-speed buffer is used to receive a signal applied to the I/O pin, the logic level of the signal may be properly recognized, but a large amount of current may be consumed. Furthermore, when a low-speed buffer is used to receive a signal applied to the I/O pin, the power consumption may be reduced, but it may be difficult to recognize the logic level of the signal inputted at high speed. Therefore, technology capable of properly recognizing high-speed and low-speed data and reducing power consumption is being developed. Such a technology may be commonly applied to not only a flash memory, but also all kinds of integrated circuits receiving a high-speed signal or low-speed signal through the same pin.
FIG. 1A illustrates an inverter-type buffer which is one of low-speed buffers. FIG. 1B illustrates an amplifier-type buffer which is one of high-speed buffers.
Referring to FIG. 1A, the inverter-type buffer includes a plurality of PMOS transistors 101, 102, 104, and 105, and a plurality of NMOS transistors 103, 106, and 107.
When an off/off signal ON/OFF is at a logic low level, the PMOS transistors 101 and 104 are turned on to enable the inverter-type buffer.
In such a state that the inverter-type buffer is enabled, when an input signal IN has a logic high level, the NMOS transistor 103 and the PMOS transistor 105 are turned on, and an output signal OUT of the buffer becomes high. Furthermore, when the input signal IN has a logic low level, the PMOS transistor 102 and the NMOS transistor 106 are turned on, and the output signal OUT of the buffer becomes low. Since such an inverter-type buffer consumes current only when a signal is inputted, the inverter-type buffer consumes a small amount of current, but may not properly recognize the logic value of a signal inputted at high speed, that is, a signal having a small swing width. FIG. 1A illustrates the structure of the most basic inverter-type buffer, and the inverter-type buffer may have a variety of structures different from that of FIG. 1A.
Referring to FIG. 1B, the amplifier-type buffer has a differential amplifier structure which detects a potential difference between an input signal IN and a reference voltage VREF. Two PMOS transistors 108 and 109 form a current mirror structure such that the same current is supplied to two nodes A and B, and voltages of the two nodes A and B are differentially amplified by a potential difference between a reference voltage VREF and an input signal IN which are inputted to NMOS transistors 110 and 111, respectively. Accordingly, when the input signal IN has a higher voltage level than the reference voltage VREF, an output signal OUT has a logic high level, and when the input signal IN has a lower voltage level than the reference voltage VREF, the output signal OUT has a logic low level. An NMOS transistor 112 receiving an on/off signal ON/OFF is turned on when the on/off signal is at a logic high level. When the NMOS transistor 112 is turned on, the buffer is enabled, and when the NMOS transistor 112 is turned off, the buffer is disabled. Accordingly, the amplifier-type buffer is enabled when the on/off signal ON/OFF is at logic high level.
Such an amplifier-type buffer may accurately recognize the logic value of an input signal IN even when the input signal IN has a small swing width, that is, the input signal IN is applied at high speed. However, since current always flows in the buffer while the buffer is enabled, a large amount of current may be consumed. FIG. 1B illustrates the structure of the most basic amplifier-type buffer, and the amplifier-type buffer may have a variety of structures different from that of FIG. 1B.